1. Field of the Invention
The present invention relates to a clamp circuit, a semiconductor device, a signal processing system, and a signal clamping method. More specifically, the present invention relates to a clamp circuit, a semiconductor device, a signal processing system, and a signal clamping method, for clamping a video signal.
2. Description of the Related Art
In general, a clamp circuit used in an analog front-end for processing a video signal, is known. The clamp circuit adds a direct-current component to a video signal waveform, and fixes a predetermined portion of the waveform to a constant voltage. The clamp circuit is configured to include an input capacitor, a constant-current source, and a comparator. The comparator compares a given reference voltage with a terminal voltage, and connects the constant-current source and the input capacitor to charge the input capacitor, when the terminal voltage is lower than the reference voltage.
FIG. 2 illustrates an example of a video signal. The video signal includes a synchronization signal, a burst signal, and an image signal. When the video signal as shown in FIG. 2 is input, the clamp circuit charges so that the synchronization signal having the lowest voltage becomes equal to the reference voltage, and clamps the synchronization signal. When the level of the synchronization signal reaches the reference voltage, a normal image signal is output. Note that, for example, Japanese Patent Application Laid-Open (JP-A) No. 2011-4071 discloses such a clamp circuit.
The configuration of a basic clamp circuit is illustrated in FIG. 20. A clamp circuit 1030 illustrated in FIG. 20 is configured to include a comparator, a clamp current source, and a control switch.
The operation of the clamp circuit 1030 illustrated in FIG. 20 will be described. The control switch connects an input terminal and a clamp current source. When the switch is turned ON, current is supplied to the input capacitor. The comparator compares the input terminal voltage with a reference voltage, and turns the switch into ON state when the input terminal voltage is lower than the reference voltage. On the other hand, when the input terminal voltage is higher than the reference voltage, the switch is turned to OFF state.
However, in this method, when the input terminal voltage in a synchronization period is lower than the reference voltage, and a burst signal in the period other than the synchronization period or the input terminal voltage in a image signal period is higher than the reference voltage, charging is performed only during the synchronization period and not during the other periods. For example, in a case of NTSC video signal used in Japan or other countries, the period of a horizontal synchronization signal is 63.5 μs, and the synchronization period is about 4.5 μs. Accordingly, a charging period becomes 7.1% (=4.5 μs/63.5 μs), and therefore, the charging period per cycle is short. Accordingly, numbers of cycles for completing the charging is necessary, and therefore, the charging time (the time from the start to completion of charging) increases.
Regarding the above, the charging time may be shortened by decreasing the capacitance of the input capacitor.
Further, the charging time may be shortened by increasing a clamp current (a current supplied to charge the input capacitor) (for example, see JP-A No. 5-292345).
However, when the capacitance of the input capacitor is decreased, the sagging (variation) of the input terminal during clamping increases, and the stability of the input terminal voltage against noise decreases.
Further, as the technique disclosed in JP-A No. 5-292345, when the charging time is shortened by increasing the clamp current, since the clamp current flows outside toward the signal source, a voltage drop occurs in relation to the impedance of the signal source. This voltage drop increases the input terminal voltage and the voltage does not drop when the clamp current stops. As a result, the input terminal voltage and the voltage of the signal source change. If the clamp current is large, since the signal source voltage greatly changes, difference between a synchronization signal level and a target clamp voltage increases.